Improved RISC Architecture
130 powerful instructions
General Purpose 32 × 8 Registers
Fully static operation
Up to 16 MIPS at 16 MHz
Multiplier in 2 cycles on the chip
High endurance non-volatile memory segments
8 KB of in-situ auto-programmable flash memory
EEPROM 512bytes
SRAM 1Ko internal
Data storage: 20 years at 85 ° C / 100 years at 25 ° C
Optional boot code section with independent locking bits
Programming in-situ by the on-chip startup program
Real read-write operation
Programming Lock for Software Security
Device Features
Real time counter with separate oscillator
Three PWM channels
Six channels, 10-bit precision
2-wire serial interface byte oriented
